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NT256D64S88ABG 256MB : 32M x 64 PC2700 Unbuffered DIMM 184pin One Bank Unbuffered DDR SDRAM MODULE Based on DDR333 32Mx8 SDRAM Features
* 184-Pin Unbuffered 8-Byte Dual In-Line Memory Module * 32Mx64 Double Data Rate (DDR) SDRAM DIMM * Performance: PC2700 Speed Sort DIMM CAS Latency f CK Clock Frequency t CK Clock Cycle f DQ DQ Burst Frequency 2.5 166 6 333 -6 2 133 7.5 266 MHz ns MHz Unit * DRAM DLL aligns DQ and DQS transitions with clock transitions. * Address and control signals are fully synchronous to positive clock edge * Programmable Operation: - DIMM CAS Latency: 2, 2.5 - Burst Type: Sequential or Interleave - Burst Length: 2, 4, 8 - Operation: Burst Read and Write * Auto-Refresh (CBR) and Self-Refresh Modes * Automatic and controlled precharge commands * 13/10/1 Addressing (row/column/bank) * 7.8 s Max. Average Periodic Refresh Interval * Serial Presence Detect * Gold contacts * SDRAMs in 66-pin TSOP Type II Package
* Intended for 100 MHz and 133 MHz applications * Inputs and outputs are SSTL-2 compatible * VDD = 2.5Volt 0.2, VDDQ = 2.5Volt 0.2 * SDRAMs have 4 internal banks for concurrent operation * Module has one physical bank * Differential clock inputs * Data is read or written on both clock edges
Description
NT256D64S88ABG is an unbuffered 184-Pin Double Data Rate (DDR) Synchronous DRAM Dual In-Line Memory Module (DIMM), organized as a one-bank high-speed memory array. The 32Mx64 module is a single-bank DIMM that uses eight 32Mx8 DDR SDRAMs in 400 mil TSOP packages. The DIMM achieves high-speed data transfer rates of up to 333MHz. The DIMM is intended for use in applications operating from 133 MHz to 166 MHz clock speeds with data rates of 266 to 333 MHz. Clock enable CKE0 controls all devices on the DIMM. Prior to any access operation, the device CAS latency and burst type/ length/operation type must be programmed into the DIMM by address inputs A0-A12 and I/O inputs BA0 and BA1 using the mode register set cycle. These DIMMs are manufactured using raw cards developed for broad industry use as reference designs. The use of these common design files minimizes electrical variation between suppliers. The DIMM uses serial presence detects implemented via a serial EEPROM using the two-pin IIC protocol. The first 128 bytes of serial PD data are programmed and locked during module assembly. The last 128 bytes are available to the customer. All NANYA 184 DDR SDRAM DIMMs provide a high-performance, flexible 8-byte interface in a 5.25" long space-saving footprint.
Ordering Information
Part Number NT256D64S88ABG-6 Speed 166MHz (6ns @ CL = 2.5) 133MHz (7.5ns @ CL= 2) PC2700 Organization 32Mx64 Leads Gold Power 2.5V
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NT256D64S88ABG 256MB : 32M x 64 PC2700 Unbuffered DIMM Pin Description
CK0, CK1, CK2 CK0, CK1, CK2 CKE0 RAS CAS WE S0 A0-A9, A11, A12 A10/AP BA0, BA1 VREF VDDID Differential Clock Inputs Clock Enable Row Address Strobe Column Address Strobe Write Enable Chip Selects Address Inputs Address Input/Auto-precharge SDRAM Bank Address Inputs Ref. Voltage for SSTL_2 inputs VDD Identification flag. DQ0-DQ63 DQS0-DQS7, DQS9-DQS16 VDD VDDQ VSS NC SCL SDA SA0-2 VDDSPD Data input/output Bi-directional data strobes Power (2.5V) Supply voltage for DQs (2.5V) Ground No Connect Serial Presence Detect Clock Input Serial Presence Detect Data input/output Serial Presence Detect Address Inputs Serial EEPROM positive power supply (2.5V)
Pinout
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Front VREF DQ0 VSS DQ1 DQS0 DQ2 VDD DQ3 NC NC VSS DQ8 DQ9 DQS1 VDDQ CK1 CK1 VSS DQ10 DQ11 CKE0 VDDQ DQ16 DQ17 DQS2 VSS A9 DQ18 A7 VDDQ DQ19 Pin 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 Back VSS DQ4 DQ5 VDDQ DQS9 DQ6 DQ7 VSS NC NC NC VDDQ DQ12 DQ13 DQS10 VDD DQ14 DQ15 NC VDDQ NC DQ20 A12 VSS DQ21 A11 DQS11 VDD DQ22 A8 DQ23 53 54 55 56 57 58 59 60 61 Pin 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 KEY DQ32 VDDQ DQ33 DQS4 DQ34 VSS BA0 DQ35 DQ40 145 146 147 148 149 150 151 152 153 Front A5 DQ24 VSS DQ25 DQS3 A4 VDD DQ26 DQ27 A2 VSS A1 NC NC VDD NC A0 NC VSS NC BA1 Pin 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 Back VSS A6 DQ28 DQ29 VDDQ DQS12 A3 DQ30 VSS DQ31 NC NC VDDQ CK0 CK0 VSS NC A10 NC VDDQ NC KEY VSS DQ36 DQ37 VDD DQS13 DQ38 DQ39 VSS DQ44 Pin 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 Front VDDQ WE DQ41 CAS VSS DQS5 DQ42 DQ43 VDD NC DQ48 DQ49 VSS CK2 CK2 VDDQ DQS6 DQ50 DQ51 VSS VDDID DQ56 DQ57 VDD DQS7 DQ58 DQ59 VSS NC SDA SCL Pin 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 Back RAS DQ45 VDDQ S0 NC DQS14 VSS DQ46 DQ47 NC VDDQ DQ52 DQ53 NC VDD DQS15 DQ54 DQ55 VDDQ NC DQ60 DQ61 VSS DQS16 DQ62 DQ63 VDDQ SA0 SA1 SA2 VDDSPD
Note: All pin assignments are consistent for all 8-byte unbuffered versions.
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NT256D64S88ABG 256MB : 32M x 64 PC2700 Unbuffered DIMM Input/Output Functional Description
Symbol CK0, CK1, CK2 CK0, CK1, CK2 CKE0 Type (SSTL) (SSTL) (SSTL) Polarity Edge Negative Edge Active High Active Low Active Low Function address and control inputs are sampled on the rising edge of their associated clocks. The negative line of the differential pair of system clock inputs. Activates the SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low initiates the Power Down mode, or the Self-Refresh mode. Enables the associated SDRAM command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. When sampled at the positive rising edge of the clock, RAS, CAS, WE define the operation to be executed by the SDRAM. Reference voltage for SSTL-2 inputs Isolated power supply for the DDR SDRAM output buffers to provide improved noise immunity Selects which SDRAM bank is to be active. During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12) when sampled at the rising clock edge. During a Read or Write command cycle, A0-A9 defines the column address (CA0-CA9) A0 - A9 A10/AP A11, A12 when sampled at the rising clock edge. In addition to the column address, AP is used to (SSTL) invoke Auto-precharge operation at the end of the Burst Read or Write cycle. If AP is high, auto-precharge is selected and BA0/BA1 define the bank to be precharged. If AP is low, auto-precharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to pre-charge. DQ0 - DQ63 DQS0 - DQS7 DQS9 - DQS16 VDD, VSS SA0 - SA2 SDA SCL VDDSPD Supply (SSTL) (SSTL) Supply Active High Data and Check Bit input/output pins operate in the same manner as on conventional DRAMs. Data strobes: Output with read data, input with write data. Edge aligned with read data, centered on write data. Used to capture write data. Power and ground for the DDR SDRAM input buffers and core logic Address inputs. Connected to either VDD or VSS on the system board to configure the Serial Presence Detect EEPROM address. This bi-directional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be connected from the SDA bus line to VDD to act as a pullup. This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from the SCL bus time to VDD to act as a pullup. Serial EEPROM positive power supply. Positive The positive line of the differential pair of system clock inputs. All the DDR SDRAM
S0
(SSTL)
RAS, CAS, WE VREF VDDQ BA0, BA1
(SSTL) Supply Supply (SSTL)
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NT256D64S88ABG 256MB : 32M x 64 PC2700 Unbuffered DIMM Functional Block Diagram (1 Bank, 32Mx8 DDR SDRAMs)
S0 DQS0 DQS9 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS1 DQS10 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS2 DQS11 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS3 DQS12 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS
DQS4 DQS13 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQS5 DQS14 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQS6 DQS15 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQS7 DQS16 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS
D0
D4
D1
D5
D2
D6
D3
D7
BA0-BA1 A0-A13 RAS CAS CKE0 WE
BA0-BA1 : SDRAMs D0-D7 A0-A13 : SDRAMs D0-D7 RAS : SDRAMs D0-D7 CAS : SDRAMs D0-D7 CKE : SDRAMs D0-D7 WE : SDRAMs D0-D7 Serial PD VDDSPD VDD/VDDQ VREF VSS VDDID SPD D0-D7 D0-D7 D0-D7 Strap: see Note 4 * Clock Wiring Clock Input SDRAMs *CK0/CK0 2 SDRAMs *CK1/CK1 3 SDRAMs *CK2/CK2 3 SDRAMs
* Wire per Clock Loading Table/ Wiring Diagrams
SCL WP
A0 SA0
A1 SA1
A2 SA2
SDA
Notes : 1. 2. 3. 4.
DQ-to-I/O wiring is shown as recommended but may be changed. DQ/DQS/DM/CKE/S relationships must be maintained as shown. DQ, DQS, DM/DQS resistors: 22 Ohms. VDDID strap connections (for memory device VDD, VDDQ): STRAP OUT (OPEN): VDD = VDDQ STRAP IN (VSS): VDD is not equal to VDDQ.
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NT256D64S88ABG 256MB : 32M x 64 PC2700 Unbuffered DIMM Serial Presence Detect -- Part 1 of 2
32Mx64 SDRAM DIMM based on 32Mx8, 4Banks, 8K Refresh, 2.5V DDR SDRAMs with SPD
SPD Entry Value Byte Description Number of Serial PD Bytes Written during Production Total Number of Bytes in Serial PD device Fundamental Memory Type Number of Row Addresses on Assembly Number of Column Addresses on Assembly Number of DIMM Bank Data Width of Assembly Data Width of Assembly (cont') Voltage Interface Level of this Assembly DDR SDRAM Device Cycle Time at CL=2.5 DDR SDRAM Device Access Time from Clock at CL=2.5 DIMM Configuration Type Refresh Rate/Type Primary DDR SDRAM Width Error Checking DDR SDRAM Device Width DDR SDRAM Device Attr: Min CLK Delay, Random Col Access DDR SDRAM Device Attributes: Burst Length Supported DDR SDRAM Device Attributes: Number of Device Banks DDR SDRAM Device Attributes: CAS Latencies Supported DDR SDRAM Device Attributes: CS Latency DDR SDRAM Device Attributes: WE Latency DDR SDRAM Device Attributes: DDR SDRAM Device Attributes: General Minimum Clock Cycle at CL=2 Maximum Data Access Time from Clock at CL=2 Minimum Clock Cycle Time at CL=1 Maximum Data Access Time from Clock at CL=1 Minimum Row Precharge Time (tRP) Minimum Row Active to Row Active delay (tRRD) Minimum RAS to CAS delay (tRCD) Minimum RAS Pulse Width (tRAS) Module Bank Density Address and Command Setup Time Before Clock Address and Command Hold Time After Clock Data Input Setup Time Before Clock Data Input Hold Time After Clock Reserved SPD Revision Checksum Data DDR333 -6 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36-61 62 63 128 256 SDRAM DDR 13 10 1 X64 X64 SSTL 2.5V 6ns 0.7ns Non-Parity SR/1x(7.8s) X8 N/A 1 Clock 2,4,8 4 2/2.5 0 1 Differential Clock +/-0.2V Voltage Tolerance 7.5ns 0.7ns N/A N/A 18ns 12ns 18ns 42ns 256MB 0.75ns 0.75ns 0.45ns 0.45ns Undefined Initial Serial PD Data Entry (Hexadecimal) Note DDR333 -6 80 08 07 0D 0A 01 40 00 04 60 70 00 82 08 00 01 0E 04 0C 01 02 20 00 75 70 00 00 48 30 48 2A 40 75 75 45 45 00 00 0A
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NT256D64S88ABG 256MB : 32M x 64 PC2700 Unbuffered DIMM Serial Presence Detect -- Part 2 of 2
32Mx64 SDRAM DIMM based on 32Mx8, 4Banks, 8K Refresh, 2.5V DDR SDRAMs with SPD
SPD Entry Value Byte 64-71 72 73-90 91-92 93-94 95-98 1. 2. Description Manufacturer's JEDEC ID Code Module Manufacturing Location Module Part number Module Revision Code Module Manufacturing Data Module Serial Number DDR333 -6 0B N/A N/A N/A Year/Week Code Serial Number Undefined Serial PD Data Entry (Hexadecimal) DDR333 -6 7F7F7F0B00000000 00 00 00 yy/ww 00 00 1, 2 Note
99-255 Reserved yy= Binary coded decimal year code, 0-99(Decimal), 00-63(Hex)
ww= Binary coded decimal year code, 01-52(Decimal), 01-34(Hex)
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NT256D64S88ABG 256MB : 32M x 64 PC2700 Unbuffered DIMM Absolute Maximum Ratings
Symbol VIN, VOUT VIN VDD VDDQ TA TSTG PD IOUT Note: Parameter Voltage on I/O pins relative to Vss Voltage on Input relative to Vss Voltage on VDD supply relative to Vss Voltage on VDDQ supply relative to Vss Operating Temperature (Ambient) Storage Temperature (Plastic) Power Dissipation Short Circuit Output Current Rating -0.5 to VDDQ+0.5 -0.5 to +3.6 -0.5 to +3.6 -0.5 to +3.6 0 to+70 -55 to +150 8 50 Units V V V V C C W mA
Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is
stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Capacitance
Parameter Input Capacitance: CK0, CK0, CK1, CK1, CK2, CK2 Input Capacitance: A0-A11, BA0, BA1, WE, RAS, CAS, CKE0, S0 Input Capacitance: SA0-SA2, SCL Input/Output Capacitance DQ0-63; DQS0-7, 9-16 Symbol CI1 CI2 CI4 CIO1 Max. 12 30 9 7 Units pF pF pF pF Notes 1 1 1 1, 2
Input/Output Capacitance: SDA CIO3 11 pF 1. VDDQ = VDD = 2.5V 0.2V, f = 100 MHz, TA = 25 C, VOUT (DC) = VDDQ/2, VOUT (Peak to Peak) = 0.2V. 2. DQS inputs are grouped with I/O pins reflecting the fact that they are matched in loading to DQ and DQS to facilitate trace matching at the board level.
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NT256D64S88ABG 256MB : 32M x 64 PC2700 Unbuffered DIMM DC Electrical Characteristics and Operating Conditions
(TA = 0 C ~ 70 C; VDDQ = 2.5V 0.2V; VDD = 2.5V 0.2V, See AC Characteristics) Symbol Parameter Supply Voltage I/O Supply Voltage Supply Voltage, I/O Supply Voltage I/O Reference Voltage I/O Termination Voltage (System) Input High (Logic1) Voltage Input Low (Logic0) Voltage Input Voltage Level, CK and CK Inputs Input Differential Voltage, CK and CK Inputs Input Leakage Current Any input 0V VIN VDD; (All other pins not under test = 0V) Output Leakage Current (DQs are disabled; 0V Vout VDDQ Output High Current (VOUT = VDDQ -0.373V, min VREF, min VTT) Output Low Current (VOUT = 0.373, max VREF, max VTT) Min 2.3 2.3 0 0.49 x VDDQ VREF - 0.04 VREF + 0.15 -0.3 -0.3 0.30 -5 Max 2.7 2.7 0 0.51 x VDDQ VREF + 0.04 VDDQ + 0.3 VREF- 0.15 VDDQ + 0.3 V DDQ + 0.6 5 Units V V V V V V V V V uA 1, 2 1, 3 1 1 1 1, 4 1 Notes 1 1
VDD VDDQ
VSS, VSSQ VREF VTT VIH (DC) VIL (DC) VIN (DC) VID (DC) II
IOZ
-5
5
uA
1
IOH
-16.8
-
mA
1
IOL
16.8
-
mA
1
1. Inputs are not recognized as valid until VREF stabilizes. 2. VREF is expected to be equal to 0.5 VDDQ of the transmitting device, and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed 2% of the DC value. 3. VTT is not applied directly to the DIMM. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF. 4. VID is the magnitude of the difference between the input level on CK and the input level on CK.
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NT256D64S88ABG 256MB : 32M x 64 PC2700 Unbuffered DIMM AC Characteristics
(Notes 1-5 apply to the following Tables; Electrical Characteristics and DC Operating Conditions, AC Operating Conditions, Operating, Standby, and Refresh Currents, and Electrical Characteristics and AC Timing.) 1. All voltages referenced to VSS. 2. Tests for AC timing, IDD, and electrical, AC and DC characteristics, may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. Outputs measured with equivalent load. Refer to the AC Output Load Circuit below. 4. AC timing and IDD tests may use a VIL to VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK, CK), and parameter specifications are guaranteed for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals is 1V/ns in the range between VIL (AC) and VIH (AC) unless otherwise specified. 5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver effectively switches as a result of the signal crossing the AC input level, and remains in that state as long as the signal does not ring back above (below) the DC input LOW (HIGH) level.
AC Output Load Circuits
VTT 50 ohms Output VOUT 30 pF Timing Reference Point
AC Operating Conditions
(TA = 0 C ~ 70 C; VDDQ = 2.5V 0.2V; VDD = 2.5V 0.2V, See AC Characteristics) Symbol VIH (AC) VIL (AC) VID (AC) VIX (AC) Parameter/Condition Input High (Logic 1) Voltage. Input Low (Logic 0) Voltage. Input Differential Voltage, CK and CK Inputs Input Differential Pair Cross Point Voltage, CK and CK Inputs 0.62 (0.5*VDDQ) - 0.2 Min V REF + 0.31 V REF - 0.31 V DDQ + 0.6 (0.5*VDDQ) + 0.2 Max Unit V V V V Notes 1, 2 1, 2 1-3 1, 2, 4
1. Input slew rate = 1V/ ns. 2. Inputs are not recognized as valid until V REF stabilizes. 3. VID is the magnitude of the difference between the input level on CK and the input level on CK. 4. The value of VIX is expected to equal 0.5*V DDQ of the transmitting device and must track variations in the DC level of the same.
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NT256D64S88ABG 256MB : 32M x 64 PC2700 Unbuffered DIMM Operating, Standby, and Refresh Currents
(TA = 0 C ~ 70 C; VDDQ = 2.5V 0.2V; VDD = 2.5V 0.2V, See AC Characteristics) Symbol I DD0 Parameter/Condition Operating Current : one bank; active / precharge; tRC = tRC (MIN) ; tCK = tCK (MIN) ; DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle Operating Current : one bank; active / read / precharge; Burst = 2; I DD1 tRC = tRC (MIN) ; CL=2.5; tCK = tCK (MIN) ; IOUT = 0mA; address and control inputs changing once per clock cycle I DD2P I DD2N I DD3P Precharge Power-Down Standby Current : all banks idle; power-down mode; CKE VIL (MAX) ; tCK = tCK (MIN) Idle Standby Current : CS VIH (MIN) ; all banks idle; CKE VIH(MIN) ; tCK = tCK (MIN) ; address and control inputs changing once per clock cycle Active Power-Down Standby Current : one bank active; power-down mode; CKE VIL (MAX) ; tCK = tCK (MIN) Active Standby Current : one bank; active / precharge; CS VIH (MIN) ; I DD3N CKE VIH (MIN) ; tRC = tRAS (MAX) ; tCK = tCK (MIN) ; DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle Operating Current : one bank; Burst = 2; reads; continuous burst; I DD4R address and control inputs changing once per clock cycle; DQ and DQS outputs changing twice per clock cycle; CL = 2.5; tCK = tCK (MIN) ; IOUT = 0mA Operating Current : one bank; Burst = 2; writes; continuous burst; I DD4W address and control inputs changing once per clock cycle; DQ and DQS inputs changing twice per clock cycle; CL=2.5; tCK = tCK (MIN) I DD5 I DD6 Auto-Refresh Current : t RC = t RFC (MIN) t RC = 7.8 s 1360 132 24 TBD mA mA mA mA 1, 2 1, 2, 4 1-3 1 1200 mA 1, 2 1320 mA 1, 2 480 mA 1, 2 200 280 200 mA mA mA 1, 2 1, 2 1, 2 TBD mA 1, 2 680 mA 1, 2 PC2700 Unit Notes
Self-Refresh Current : CKE 0.2V Operating Current: four bank; four bank interleaving with BL = 4, address and control inputs randomly changing; 50% of data changing at every I DD7 transfer; tRC = tRC (min); IOUT = 0mA. 1. I DD specifications are tested after the device is properly initialized. 2. Input slew rate = 1V/ ns. 3. Enables on-chip refresh and address counters. 4. Current at 7.8 s is time averaged value of IDD5 at tRFC (MIN) and IDD2P over 7.8 s.
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NT256D64S88ABG 256MB : 32M x 64 PC2700 Unbuffered DIMM AC Timing Specifications for DDR SDRAM Devices Used on Module
(TA = 0 C ~ 70 C; VDDQ = 2.5V 0.2V; VDD = 2.5V 0.2V, See AC Characteristics) (Part 1 of 2) Symbol tAC tDQSCK tCH tCL tCK tCK tDH tDS tDIPW tHZ tLZ tDQSQ tDQSQA tHP tQHS tQH tDQSS tDQSL,H tDSS tDSH tMRD tWPRES tWPST tWPRE tIH tIS tIH tIS Parameter DQ output access time from CK/CK DQS output access time from CK/CK CK high-level width CK low-level width Clock cycle time DQ and DM input hold time DQ and DM input setup time DQ and DM input pulse width (each input) Data-out high-impedance time from CK/CK Data-out low-impedance time from CK/CK DQS-DQ skew (DQS & associated DQ signals) DQS-DQ skew (DQS & all DQ signals) Minimum half clk period for any given cycle; defined by clk high (tCH ) or clk low (tCL ) time Data Hold Skew Factor Data output hold time from DQS Write command to 1st DQS latching transition DQS input low (high) pulse width (write cycle) DQS falling edge to CK setup time (write cycle) DQS falling edge hold time from CK (write cycle) Mode register set command cycle time Write preamble setup time Write postamble Write preamble Address and control input hold time (fast slew rate) Address and control input setup time (fast slew rate) Address and control input hold time (slow slew rate) Address and control input setup time (slow slew rate) min (tCH, tCL) 0.55 tHP - tQHS 0.75 0.35 0.2 0.2 12 0 0.40 0.25 0.75 0.75 0.8 0.8 0.60 1.25 CL=2.5 CL=2 -6 Min. -0.7 -0.7 0.45 0.45 6 7.5 0.45 0.45 1.75 -0.7 -0.7 +0.7 +0.7 0.4 0.4 Max. +0.7 +0.7 0.55 0.55 12 12 Unit ns ns tCK tCK ns ns ns ns ns ns ns ns ns tCK Ns tCK tCK tCK tCK tCK ns ns tCK tCK ns ns ns ns 1-4 1-4 1-4 1-4 1-4 1-4 1-4, 7 1-4, 6 1-4 2-4, 9, 11, 12 2-4, 9, 11, 12 2-4, 10-12, 14 2-4, 10-12, 14 Notes 1-4 1-4 1-4 1-4 1-4 1-4 1-4, 15, 16 1-4, 15, 16 1-4 1-5 1-5 1-4 1-4 1-4
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NT256D64S88ABG 256MB : 32M x 64 PC2700 Unbuffered DIMM AC Timing Specifications for DDR SDRAM Devices Used on Module
(TA = 0 C ~ 70 C; VDDQ = 2.5V 0.2V; VDD = 2.5V 0.2V, See AC Characteristics) (Part 2 of 2) Symbol tIPW tRPRE tRPST tRAS tRC tRFC tRCD tRAP tRP tRRD tWR tDAL tWTR tXSNR tXSRD tREFI Input pulse width Read preamble Read postamble Active to Precharge command Active to Active/Auto-refresh command period Auto-refresh to Active/Auto-refresh command period Active to Read or Write delay Active to Read Command with Auto-precharge Precharge command period Active bank A to Active bank B command Write recovery time Auto precharge write recovery + recharge time Internal write to read command delay Exit self-refresh to non-read command Exit self-refresh to read command Average Periodic Refresh Interval Parameter -6 Min. 2.2 0.9 0.40 42 60 72 18 18 18 12 15 (tWR/tCK) + (tRP/tCK) 1 75 200 7.8 1.1 0.60 120,000 Max. Unit ns tCK tCK ns ns ns ns ns ns ns ns tCK tCK ns tCK s Notes 2-4, 12 1-4 1-4 1-4 1-4 1-4 1-4 1-4 1-4 1-4 1-4 1-4, 13 1-4 1-4 1-4 1-4, 8
REV 1.1
08/2002
12
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
(c) NANYA TECHNOLOGY CORP.
NT256D64S88ABG 256MB : 32M x 64 PC2700 Unbuffered DIMM AC Timing Specification Notes
1. Input slew rate = 1V/ns. 2. The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals other than CK/CK is VREF. 3. Inputs are not recognized as valid until VREF stabilizes. 4. The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (Note 3) is VTT. 5. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ). 6. The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 7. The specific requirement is that DQS be valid (high, low, or some point on a valid transition) on or before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from high to low at this time, depending on tDQSS. 8. A maximum of eight Auto refresh commands can be posted to any given DDR SDRAM device. 9. For command/address input slew rate >= 1.0 V/ns. Slew rate is measured between VOH (AC) and VOL (AC). 10. For command/address input slew rate >= 0.5 V/ns and < 1.0 V/ns. Slew rate is measured between VOH (AC) and VOL (AC). 11. CK/CK slew rates are >= 1.0 V/ns. 12. These parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guaranteed by design or tester characterization. 13. For each of the terms in parentheses, if not already an integer, round to the next highest integer. t CK is equal to the actual system clock cycle time. For example, for PC2100 at CL= 2.5, t DAL = (15ns/7.5ns) +(20ns/7.0ns) = 2 + 3 = 5. 14. An input setup and hold time derating table is used to increase t IS and t IH in the case where the input slew rate is below 0.5 V/ns. Input Slew Rate 0.5 V/ns 0.4 V/ns Delta (tIS) 0 +50 Delta (tIH) 0 0 Unit ps ps Note 1, 2 1, 2
0.3 V/ns +100 0 ps 1, 2 1. Input slew rate is based on the lesser of the slew rates determined by either V IH (AC) to V IL (AC) or V IH (DC) to V IL (DC), similarly for rising transitions. 2. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device. 15. An input setup and hold time derating table is used to increase t DS and t DH in the case where the I/O slew rate is below 0.5 V/ns. Input Slew Rate 0.5 V/ns 0.4 V/ns Delta (tDS) 0 +75 Delta (tDH) 0 +75 Unit ps ps Note 1, 2 1, 2
0.3 V/ns +150 +150 ps 1, 2 1. I/O slew rate is based on the lesser of the slew rates determined by either V IH (AC) to V IL (AC) or V IH (DC) to V IL (DC), similarly for rising transitions. 2. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device. 16. An I/O Delta Rise, Fall Derating table is used to increase t DS and t DH in the case where DQ, DM, and DQS slew rates differ. Delta Rise and Fall Rate 0.0 ns/V 0.25 ns/V Delta (tDS) 0 +50 Delta (tDH) 0 +50 Unit ps ps Note 1-4 1-4
0.5 ns/V +100 +100 ps 1-4 1. Input slew rate is based on the lesser of the slew rates determined by either V IH (AC) to V IL (AC) or V IH (DC) to V IL (DC), similarly for rising transitions. 2. Input slew rate is based on the larger of AC to AC delta rise, fall rate and DC to DC delta rise, fall rate. 3. The delta rise, fall rate is calculated as: [1/(slew rate 1)] - [1/(slew rate 2)] For example: slew rate 1 = 0.5 V/ns; slew rate 2 = 0.4 V/ns. Delta rise, fall = (1/0.5) - (1/0.4) [ns/V] = -0.5 ns/V Using the table above, this would result in an increase in t DS and t DH of 100 ps. 4. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device.
REV 1.1
08/2002
13
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
(c) NANYA TECHNOLOGY CORP.
NT256D64S88ABG 256MB : 32M x 64 PC2700 Unbuffered DIMM Package Dimensions
FRONT
133.35 5.250 128.93 5.076 (2x)4.00 0.157
10.0 0.394
0.098
Detail A
Detail B
2.30 0.91
2.50
BACK
3.18 0.125 MAX
Detail A 3.80 0.150 4.00 0.157
Detail B 1.00 Width 0.039
1.27+/- 0.10 0.050 +/- 0.004
6.35 0.250 1.80 0.071
1.27 Pitch 0.05
Note: All dimensions are typical with tolerances of +/- 0.15 (0.006) unless otherwise stated. Units: Millimeters (Inches)
REV 1.1
08/2002
14
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
(c) NANYA TECHNOLOGY CORP.
17.80 0.700
Side
31.75 1.250
NT256D64S88ABG 256MB : 32M x 64 PC2700 Unbuffered DIMM Revision Log
Rev 1.0 1.1 Date 07/2002 08/2002 Official Release Added tolerance specification of +/- 0.15 to Package Dimensions Modification
REV 1.1
08/2002
15
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
(c) NANYA TECHNOLOGY CORP.

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